Switching circuits employing esaki diodes



United States Patent Ofifice 3,348,933 Patented Oct. 17, 1967 3,348,033SWITCHiN G CIRCUITS EMPLOYING ESAKI DIODES Algirdas J. Gruodis, EastHaven, Conn., and Lawrence K. Lange, Wappingers Fails, and Wiliiam H.McAnney, Ponghkeepsie, N.Y., assignors to International BusinessMachines Corporation, Armonk, N.Y., a corporation of New York Originalapplication Apr. 17, 1961, Ser. No. 1033,3374, now Patent No. 3,230,387,dated Jan. 18, 1966. Divided and this application Aug. 10, 1965, Ser.No. 478,585

3 Ciaims. (Cl. 235-175) ABSTRACT OF THE DISCLOSURE A switching circuitincluding a signal source capable of supplying signals of three levelsof magnitude, a transistor amplifier having a base terminal, and anegative resistance diode having a high conductivity state for a lowapplied voltage and a'low conductivity state for a high applied voltageconnected between said base terminal and said signal source, wherebysignals of said first magnitude switch said diode to its highconductivity state and activate said amplifier, signals of said secondmagnitude switch said negative resistance diode to said low conductivitystate and said amplifier is not activated, and signals of said thirdmagnitude force enough current through said diode in said lowconductivity state to activate said amplifier.

This application is a division of an application of Algirdas J. Gruodis,Lawrence K. Lange, and William H. McAnney, Ser. No. 103,374, filed Apr.17, 1961, now Patent No. 3,230,387, and entitled, Switching CircuitsEmploying Esaki Diodes.

This invention relates to digital computing circuits and moreparticularly to such circuits employing Esaki diodes.

It is well known that circuits for performing logical operations indigital computers become more expensive as the logical operation to beperformed becomes more complex. A greater number of switching elementsare required to perform the logic. Also, where more than one inputsignal is to be acted upon by the circuit a greater number of switchingelements are required in order to accept these additional input signals.Using the technique taught in the present invention the number ofswitching elements required to perform a given logical operation isreduced. Also, the present invention is capable of accepting a pluralityof input signals without the use of additional switchingelements,'thereby reducing the expense of the circuit.

Circuits which require a large number of switching elements usuallyperform the logical operations slowly. Frequently the input signal musttravel through many stages of switching elements before reaching theoutput. Each stage inserts a delay since the operation of one stagecannnot begin until the elements in the previous stage have completedswitching. In the present invention the number of stages required for agiven operation is reduced.

Accordingly it is an object of the present invention to provideswitching circuits capable of performing logical operations usingrelatively few switching elements.

It is another object of the present invention to provide switchingcircuits with relatively few stages of delay.

In accordance with the foregoing objects, the invention utilizes theunique characteristics of the Esaki diode.

The Esaki diode has a high state of conduction and a low state ofconduction as opposed to conventional switching elements, such astransistors, which have only a single state of conduction. In thepresent invention the Esaki diode controls the current supplied toconventional switching elements. Due to the Esaki diodes bistablecharacteristic more complicated logical operations can be performed witha given number of switching elements than could be performed using onlyconventional switching elements.

Further, the conduction in the Esaki diode depends upon the degree ofsignal amplitude applied thereto, as opposed to the conduction inconventional switching elements which depends merely upon the presenceor absence of a signal. In the present invention a plurality of signalsare combined using inexpensive passive networks to form a single signalwhose amplitude is representative of the number of signals so combined.An advantageous feature of the present invention is the ability of theEsaki diode to switch conductivity states dependent upon the amplitudeof the combined signals applied hereto, and to control conventionalswitching elements. Therefore, conventional switching elements may bereplaced 'by relatively low cost passive networks resulting in a savingin expense and a saving in time since passive elements insert noswitching time delay into the circuit.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings.

In the drawings:

FIG. 1 is an electrical schematic of a full adder embodying the presentinvention.

FIG. 2 is a current-voltage characteristic of an Esaki diode.

FIG. 3 is a diagram of input and output pulses for the electricalschematic shown in FIG. 1.

FIG. 4 is an electrical schematic of a parity checker, or Exclusive ORcircuit embodying the present invention.

Shown in FIG. 1 is a full adder circuit for adding the input signals A-Capplied to terminals 5-7 and providing the inverted SUM output signal onterminal 8 and the inverted CARRY output signal on terminal 9. The inputsignals A and B represent the two binary digits to be added. The inputsignal C represents the carry from the next lower order bit position.

The circuit in FIG. 4 may be used as either a parity checker or anExclusive OR circuit in a digital computer. The circuit of FIG. 4 iscapable of accepting up to three signals on terminals 11-13 andproviding a signal on terminal 14 which is identical to the signalprovided on terminal 8 in FIG. 1. The signal on terminal 14 is usefulbecause it performs a parity check upon the signals applied to theterminals 11-13 and is also representative of the Exclusive OR functionof these signals as Will be described in detail below.

Referring to FIG. 1, the Esaki diode 20 is a preferred negativeresistance circuit elements to be used in the present invention. Thediode is described in an article entitled New Phenomenon in NarrowGermanium PN Junctions, Physical Review, vol. 109, 1958, pages 603 and604, by L. Esaki. Although the Esaki diode, mso called the Tunnel diode,is preferred, it should be understood that there are other negativeresistance circuit elements which could be employed in the presentinvention with satisfactory results. The remaining paragraphs of thedescription, however, will be limited to switching circuits employingEsaki diodes for convenience in explanation.

The current voltage characteristic for an Esaki diode is shown in FIG.2. The operation of an Esaki diode is unique, in that as the voltageacross the diode is increased the current increases rapidly until a peakvalue represented by the point 21 is reached. This region of the curveis called the high conductivity state. As the voltage across the diodeincreases past the point 21, the current decreases until the point 22 isreached. This region is known as the negative resistance region of thediode. Further increase in the voltage across the diode past the point22 causes the current to begin increasing again. This last-mentionedregion is called the low conductivity state.

The Esaki diode 20 is connected between a junction 24 and base 25 oftransistor 26. Base 27 of transistor 28 is coupled to junction 24 byresistor 29. Resistors 31-34 form a network for coupling the outputs ofgates 35-37 to the junction 24. The gates 35-37 apply the positivevoltage supply on terminal 38 to the network 31-34 when a signal isapplied upon terminals -7. For example when the signal A is present onterminal 5, the gate 35 is activated and the voltage on terminal 38 isapplied to the resistor 31.

The current supplied to junction 24 by the network 31-34 is representedby the waveform 39 in FIG. 3. At time Til none of the signals A-C arepresent on terminals 5-7. At time T1 one of the three signals ispresent; at time T2 two of the three signals are present; and at time T3all of the signals are present. The waveform 39 increases in magnitudefor each additional input signal applied.

' Operation of Esaki diode 20 and transistors 26 and 28 may be describedwith reference to the current-voltage characteristic shown in FIG. 2. Attime T0 the current flowing through Esaki diode 20 is zero so thattransistor 26 is not conducting. The resistor 49 connects the base V 25to ground 41. At this time the voltage on terminal 8 approaches thevoltage of the positive supply on terminal 42. The output on terminal 8is represented by the waveform 46. The current into junction 24 is zeroat time T0 and therefore no current is coupled through resistor 29 tothe base 27. Transistor 28 is not conducting at this time since the base27 is connected to ground 43 by resistor 44. The voltage on outputterminal 9 approaches the voltage of the positive supply on terminal 45represented by the waveform at time Ti).

The load lines 51-53 are determined by the power supply on terminal 38,and the resistors 29,- 31-34, 40 and 44. At time T1 the current throughthe Esaki diode 20 is represented by the point 1 in FIG. 2. Thismagnitude of current exceeds that which is sufiicient to cause thetransistor 26 to conduct. The magnitude of current sufficient to causethe transistor 26 to conduct can be adjusted by resistor 40 and isrepresented by the dashed line 54 in FIG. 2. At time T1 the output onterminal 8 approaches the ground potential 41 represented by thewaveform 46 at time T1. At this time most of the current from junction24 is conducted through the Esaki diode 20. There is insufiicientcurrent coupled to the base 27 to cause the transistor 28 to conduct.Therefore, the waveform 55 shows the output signal on terminal 9 at thelevel approaching the positive supply connected to terminal-45.

At time T2 the Esaki diode is switched to the low conductivity state.The current passing through the diode is represented by the point t Atthis time the current through the Esaki diode 26 is below the magnituderepresented by the line 54 and therefore is insufficient to causetransistor 26 to conduct. The output on terminal 8 rises as shown inFIG. 3 by the waveform 46 at time T2. The current flowing out of thejunction 24 now takes the path through resistor 29 to the base 27because the high impedance of the Esaki diode 26 now in the lowconductivity state blocks the current. The resistor 44 can be adjustedso that this amount of current is suflicient to cause transistor 28 toconduct. Therefore, at time T2 as represented by the waveform 55, thevoltage on terminal 9 approaches the level of ground 43.

The point t in FIG. 2 represents the current flowing through the Esakidiode at time T3. This current exceeds the magnitude represented by theline 54- and is sufficient to cause the transistor 26 to conduct. Sincethe Esaki diode is in the low conductivity state a portion of thecurrent flowing into the junction 24 takes the path through the resistor29 to the base 27 and is sufiicient to cause transistor 28 to conduct.

The outputs generated on the terminals 8 and 9, as described above,represent the inverted sum and carry functions respectively. This can beshOWn by writing the Boolean algebra expression for the signalsgenerated on the terminals 8 and 9. Boolean algebra is described in thetext Arithmetic Operations in Digital Computers by R. K. Richards, VanNostrand Company, Inc. The expression at the terminal 8 is an algebraicstatement of when the voltage on this terminal approaches the voltage ofthe positive supply on terminal 42 as a function of the presence andabsence of the signals A-C on terminals 5-7. The first term of theexpression, K-B-E, represents the condition at the time Ti). That is,when all of the signals A-C are absent the more positive signal ispresent on output terminal 8. The next three term of the Booleanexpression A-B-E-j-A-B-C-i-K-B-C represent the three possiblevariationsof the input signals which result in the operation describedat time T2. That is, when any two of the signals A-C are present,terminal 8 is positive. The entire expression K-B-E-lA-B-( )+K-B-C+A-B-Ccan be rewritten as A-BC-j-K-B-C-l-K-B-E-j-A-B-fi which is the familiarexpression of the SUM function inverted.

In a like manner the Boolean expression at the output terminal 9 can berewritten as A-B-C+K-B-C+A- I-C+A'B-'C J which is the familiar CARRYfunction inverted.

The circuit of FIG. 4 is identical to that shown in FIG. 1 with theexception of transistor 28 and coupling resistor 29 which have beenremoved. The operation of the circuit is the same, and the Booleanexpression for the output on terminal 14 is identical to that shown atterminal 3. This output signal is useful because it performs a paritycheck upon the input signals A-C. That is, the signal is present onterminal 14 when the number of inputs present on terminals 11-13 iseven. For example, when there are no inputs on terminals 11-13 theoutput is present on terminal 14 indicating an even parity (zero) ofinputs. When any two of the inputs are present on terminals 11-13 thesignal on terminal 14 is present indicating that there is an even parity(two) of inputs. However, when all three inputs are present thetransistor 61 conducts and the output signal on terminal 14 approachesthe lower potential of ground 62. Likewise when any one of the threeinput signals A-C is present the transistor 61 conducts and the signalon output terminal 14 is absent indicating that an odd parity exists. 7L

A two-way Exclusive OR circuit can be made by eliminating the terminal13, gate 63, and resistor 64 from the V circuit shown in FIG. 4. Thethree possible operating conditions of this circuit are represented bythe times T0, T1, and T2 in FIGS. 2 and 3. The Boolean expression at theoutput terminal 14 as a function of the signals A and B is A-B-j-A-BLWhen this expression isinverted, 7

converting means which can generate an analog representation of thesignals A-C. Another suitable signal source is a potentiometer with aslideable wiper arm. The waveform generated by this type of signalsource would be linearly increasing waveform as opposed to the stepwisewaveform 39. However, at times T0-T3 the operation of the circuit wouldbe identical to that described in response to the stepwise waveform 40.

In the embodiments of the invention shown in FIGS; 1 and 4 NPN junctiontype transistors are shown. PNP type transistors can be used byreversing the polarity of the voltage supplies on terminals 38, 42, 45,70 and 71 and by reversing the Esaki diodes 2i) and 72 so that thedirection of the current flow is into the junctions 24 and 73respectively. The waveforms 39, 46 and 55, shown in FIG. 3, are invertedfor the PNP embodiment of the full adder shown in FIG. 1. This resultsin the true form of the SUM and CARRY function generated at theterminals 8 and 9. Likewise, the true form of the Exclusive OR functionis generated on terminal 14 when the circuit of FIG. 4 is implementedwith the PNP type transistor. When the circuit of FIG. 4 is used as aparity checker, the signal on terminal 14 approaches the more positivelevel of ground 62 when the parity of the input signals A-C is odd.

From the above detailed description it can be seen that relatively fewswitching elements have been used. The outputs from gates 35-37 areconverted into a single analog representation by the resistor network31-34 without the use of switching elements and without inserting aswitching delay. This analog signal differs from the conventional binarysignal in that the magnitude of the analog signal carries information.The ability of the switching circuits of the present invention torespond to the magnitude of analog signals brings about the reduction inthe number of switching elements and the reduction in time delays.

While the invention has been particularly shown and described withreference to prefered embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formand details may be made therein without departing from the spirit andscope of the invention.

We claim:

1. A switching circuit comprising: a transistor amplifier including abase terminal; a signal source capable of supplying signals of a first,a second, and a third increasing degree of magnitude; a negativeresistance diode having a high conductivity state for a low appliedvoltage and a low conductivity state for a high applied voltageconnected between said base terminal and said signal source, wherebysignals of said first magnitude switch said negative resistance diode tosaid high conductivity state and are sufiicient to cause said transistorto conduct, sginals of said second magnitude switch said negativeresistance diode to said low conductivity state and are insufiicient tocause said transistor to conduct, and signals of said third magnitudeswitch said negative resistance diode to said low conductivity state andare sufiicient to force enough current through said diode in said wconductivity state to cause said transistor to conduct.

2. A parity checker circuit for checking the parity of three signalscomprising: a transistor amplifier including a base terminal; convertingmeans for accepting said three signals and providing an analogrepresentation thereof; a negative resistance diode having a highconductivity state for a low applied voltage and a low conductivitystate for a higher applied voltage connected between said base terminaland said converting means, whereby the presence of one of said signalsswitches said negative resistance diode to said high conductivity stateand is suflicient to cause said transistor to conduct, the presence ofany two of said signals switches said negative resistance diode to saidlow conductivity state and is insuflicient to cause said transistor toconduct, and the presence of all three of said signals switches saidnegative resistance diode to said low conductivity state and issufiicient to force enough current through said diode in said lowconductivity state to cause said transistor to conduct.

3. A full adder circuit for accepting three signals and providing a SUMand a CARRY out-put comprising: a first, and a second transistoramplifier, each having a base terminal; converting means for acceptingsaid three signals and providing at its output terminal an analogrepresentation thereof; a negative ressitance diode having a highconductivity state for a low applied voltage and a low conductivitystate for a higher applied voltage connected between the base terminalof said first transistor and said output terminal; a coupling networkconnected between the base terminal of said second transistor and saidoutput terminal, whereby the presence of one of said signals switchessaid negative resistance diode to said high conductivity state and issuificient to cause said first transistor to conduct, the presence ofany two of said signals switches said negative resistance diode to saidlow conductivity state causing said first transistor to conduct anddiverting enough current through said coupling network to cause saidsecond transistor to conduct, and the presence of all three of saidsignals switches said negative resistance diode to said low conductivitystate and is suflicient to force enough current through said diode insaid low conductivity state to cause said first transistor to conduct.

References Cited UNITED STATES PATENTS 3,194,974 7/1965 Rymaszeski307-885 3,218,483 11/1965 Clapper 30788.5

MALCOLM A. MORRISON, Primary Examiner. V. SIBER, Assistant Examiner.

1. A SWITCHING CIRCUIT COMPRISING: A TRANSISTOR AMPLIFIER INCLUDING ABASE TERMINAL; A SIGNAL SOURCE CAPABLE OF SUPPLYING SIGNALS FO A FIRST,A SECOND, AND A THIRD INCREASING DEGREE OF MAGNITUDE; A NEGATIVERESISTANCE DIODE HAVING A HIGH CONDUCTIVITY STATE FOR A LOW APPLIEDVOLTAGE AND A LOW CONDUCTIVITY STATE FOR A HIGH APPLIED VOLTAGECONNECTED BETWEEN SAID BASE TERMINAL AND SAID SIGNAL SOURCE, WHEREBYSIGNALS OF SAID FIRST MAGNITUDE SWITCH SAID NEGATIVE RESISTANCE DIODE TOSAID HIGH CONDUCTIVITY STATE AND ARE SUFFICIENT TO CAUSE SAID TRANSISTORTO CONDUCT, SIGNALS OF SAID SECOND MAGNITUDE SWITCH SAID NEGATIVERESISTANCE DIODE TO SAID LOW CONDUCTIVITY STATE AND ARE INSUFFICIENT TOCAUSE SAID TRANSISTOR TO CONDUCT, AND SIGNALS OF SAID THIRD MAGNITUDESWITCH SAID NEGATIVE RESISTANCE DIODE TO SAID LOW CONDUCTIVITY STATE ANDARE SUFFICIENT TO FORCE ENOUGH CURRENT THROUGH SAID DIODE IN SAID LOWCONDUCTIVITY STATE TO CAUSE SAID TRANSISTOR TO CONDUCT.